1. Field of the Invention
The present invention relates to a semiconductor memory device having a low power consumption mode.
2. Description of the Related Art
In recent years, the cellular phone has been given not only a function to have a vocal communication but also a function to transmit character-string data or image data. Moreover, the cellular phone has been expected in the future to become a kind of information terminal (for example, a portable type personal computer) as the internet services are diversified. Thus, the information volume of data to be handled by the cellular phone has been drastically increasing. Conventionally, the cellular phone has employed as its work memory SRAMs having a memory capacity of about 4 Mbit. The work memory is a memory for retaining the necessary data during the operation of the cellular phone. It is obvious that the memory capacity of the work memory will be short in the future.
On the other hand, the transmission speed of the cellular phone has been heightening. The smaller the cellular phone becomes, the smaller the battery to be mounted becomes. Therefore, the work memory to be employed in the cellular phone is required to have a high speed, low power consumption and a large capacity. In the cellular phone serious price competitions, it is necessary to make the costs for parts as low as possible. Therefore, the work memory has to be at low price.
The conventional SRAMs as employed in the work memory are higher per bit in cost than DRAMs. The production number of SRAMs is smaller than that of the DRAMs so that it is difficult to lower its price. Moreover, there have never been developed SRAMs having a large memory capacity (for example, 64 Mbit).
In this situation, it has been considered to replace the SRAMs by flash memories and DRAMs in the work memory of the cellular phone.
The flash memory has a power consumption as low as several xcexcW during a standby state but requires several xcexcs to several tens xcexcs for writing data. When the flash memory is employed as the work memory of the cellular phone, therefore, it is difficult to transmit/receive massive data at high speed. The flash memory performs the write operation at the unit of a sector so that it is not suitable for rewriting bit by bit image data such as the data of a moving image.
On the contrary, the DRAMs can execute both the read operation and the write operation within several tens ns and can process the data of the moving image easily. The power consumption during the standby state is higher than that of the flash memories. In the present DRAMs, the power consumption in the standby state is about 1 mW during a self-refresh mode for retaining written data and about 300 xcexcW during a standby mode not required for retaining written data.
If the power consumption during the standby mode could be reduced to that of the flash memories, the DRAMs could be employed as the work memory of the cellular phone, but such circuit technology has never been proposed.
The power consumption of the DRAMs can be reduced to zero by stopping the power supply to the DRAMs. However, since the address terminals, the data terminals and the like of the DRAMs are connected with the terminals of other electronic parts through the wiring patterns on a circuit board, it is required to drastically change the system of the cellular phone (the pattern change of the circuit board, re-layout and so on) for the termination of the power supply to the DRAMs.
Besides, there has not been proposed a technology which realizes exit from the standby mode without the malfunction of an internal circuit after the power supply is terminated to stop the operation of the internal circuit during the standby mode.
Where the internal voltage to be used in the internal circuit is generated inside of the device, it has to be quickly returned to a predetermined voltage when a release is made from a standby mode (a low power consumption mode). However, this technique has never been proposed.
An object of the present invention is to enter the device into a low power consumption mode and exit the device from a low power consumption mode with reliability.
Another object of the present invention is to provide a semiconductor memory device capable of drastically reducing current consumption during standby mode as compared with the conventional devices and a method of controlling the semiconductor memory device.
Still another object of the present invention is to provide a semiconductor memory device capable of drastically reducing current consumption during a standby period as compared with the conventional devices and a method of controlling the semiconductor memory device.
Another object of the present invention is to easily enter a device into a low power consumption mode by a control signal from the exterior.
Another object of the present invention is to prevent the feedthrough current (or leak path) of an internal circuit during a low power consumption mode.
Still another object of the present invention is to easily enter the device into the low power consumption mode by employing an existing control signal.
Another object of the present invention is to easily enter the device into the low power consumption mode by a command input.
Another object of the present invention is to easily enter the device into the low power consumption mode by a dedicated control signal.
Another object of the invention is to quickly return from the low power consumption mode.
According to one aspect of the semiconductor memory device in the present invention, an internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. When the internal voltage generator is operated, a predetermined amount of electric power is consumed. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. The internal voltage is not to be generated due to the inactivation of the internal voltage generator so that the power consumption may be reduced. In response to the control signal from the exterior, therefore, it is possible to easily enter the device into the low power consumption mode.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a booster and the generation of a boost voltage to be supplied to a word line. During the low power consumption mode the booster steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a substrate voltage generator to stop the generation of a substrate voltage to be supplied to a substrate. During the low power consumption mode, the substrate voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of an internal supply voltage generator to stop the generation of an internal supply voltage to be supplied to a memory core. During the low power consumption mode, the internal supply voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semiconductor memory device in the present invention, in response to the control signal from the exterior, the entry circuit stops the operation of a precharging voltage generator to stop the generation of a precharging voltage to be supplied to bit lines. During the low power consumption mode, the precharging voltage generator steadily consuming the electric power stops so that the power consumption is drastically reduced.
According to another aspect of the semiconductor memory device in the present invention, an external voltage supplying circuit supplies the power supply voltage as the internal voltage to the internal circuit during the low power consumption mode. When the internal voltage generating circuit is inactive, therefore, the power supply terminal of each internal circuit is supplied with a predetermined power supply voltage. As a result, each element of the internal circuit is fixed in a predetermined state to prevent a leak path. In other words, the flow of a feedthrough current is prevented.
According to another aspect of the semiconductor memory device in the present invention, a predetermined internal circuit is inactivated when a reset signal is supplied from the exterior. In response to this reset signal, the entry circuit enters the device into the low power consumption mode. During the resetting, the device need not be operated. Therefore, it can enter the low power consumption mode by utilizing the existing signal. The type and number of external terminals are identical to those of the conventional terminals so that adding the low power consumption mode does not lower the usability.
According to another aspect of the semiconductor memory device in the present invention, the entry circuit receives a plurality of control signals from the exterior. The entry circuit enters the device into the low power consumption mode when it recognizes the states of the control signals as low power consumption commands. Therefore, the device can enter the low power consumption mode by the command input.
According to another aspect of the semiconductor memory device in the present invention, the entry circuit receives a reset signal and a chip enable signal from the exterior. The entry circuit enters the device into the low power consumption mode when it recognizes the states of those control signals as low power consumption commands. Therefore, the device can enter the low power consumption mode by the command input.
According to another aspect of the semiconductor memory device in the present invention, when the reset signal is inactivated during a predetermined period and in this state the chip enable signal is activated during a predetermined period, the device enters the low power consumption mode. Even when a glitch occurs in the reset signal or the chip enable signal due to power supply noises or the like, it is able to prevent the device from erroneously entering the low power consumption mode.
According to another aspect of the semiconductor memory device in the present invention, the entry circuit receives a plurality of control signals from the exterior during the low power consumption mode. The entry circuit exits the device from the low power consumption mode when the levels of the control signals indicate exit of the low power consumption mode. Therefore, the device can be exited from the low power consumption mode by the command input.
The entry circuit enters the device into the low power consumption mode when it receives the predetermined level or the transition edge of a low power consumption mode signal. Therefore, the device can reliably enter the low power consumption mode by employing a dedicated signal.
According to another aspect of the semiconductor memory device in the present invention and controlling the semiconductor memory device, when the state of a control signal received during the low power consumption mode indicates exit of the low power consumption mode, the low power consumption mode is exited. This allows the device to be easily exited from the low power consumption mode by a control signal from the exterior. The exist from the low power consumption mode is, for example, executed by controlling the entry circuit.
According to another aspect of the semiconductor memory device in the present invention and controlling the semiconductor memory device, after the low power consumption mode is exited, a reset signal for initializing an internal circuit is activated during a period where the internal voltage is lower than a predetermined voltage. For instance, the reset signal is activated during a period where the internal voltage is lower than a reference voltage generated by stepping down the power supply voltage. Therefore, when the low power consumption mode shifts to a normal operating mode, the internal circuit can be reliably reset, which prevents malfunction of the internal circuit.
According to another aspect of the semiconductor memory device in the present invention, after the low power consumption mode is exited, a reset signal for initializing an internal circuit is activated during a period where a boost voltage internally generated is lower than a predetermined voltage. For example, the reset signal is activated during a period where the boost voltage is lower than the power supply voltage. In addition, the reset signal can be activated during a period where the boost voltage is lower than a reference voltage generated by stepping down the power supply voltage.
According to another aspect of the semiconductor memory device in the present invention, after the low power consumption mode is exited, a reset signal for initializing an internal circuit is activated during a period where at least one of the internal voltage and a boost voltage internally generated is/are lower than respective predetermined voltages. Therefore, when the low power consumption mode shifts to the normal operating mode, the internal circuit can be reliably reset, which prevents malfunction of the internal circuit.
According to another aspect of the semiconductor memory device in the present invention, at the time of the exit from the low power consumption mode, while a timer is measuring a predetermined length of time, a reset signal for initializing an internal circuit is activated. This allows reliable reset of the internal circuit, leading to preventing malfunction of the internal circuit when the low power consumption mode shifts to a normal operating mode.
According to another aspect of the semiconductor memory device in the present invention, a timer includes a CR time constant circuit. The timer measures the length of a time based on the propagation delay time of a signal propagated to the CR time constant circuit so that the activation period of a reset signal can be set by a simple circuit.
According to another aspect of the semiconductor memory device in the present invention, at the time of the exit from the low power consumption mode, a reset signal for initializing an internal circuit is activated while a counter operating in the normal operation counts a predetermined number. This allows reliable reset of the internal circuit, leading to preventing malfunction of the internal circuit when the low power consumption mode shifts to a normal operating mode. For example, a refresh counter for indicating the refresh address of memory cells or the like is employed as a counter.
According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, a self-refresh control circuit automatically refreshes memory cells at a predetermined cycle. An internal voltage generator generates an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from the exterior. The semiconductor memory device when receiving a control signal from the exterior, inactivates the self-refresh control circuit and lowers the supply capability of the internal voltage generator, thereby entering into a low power consumption mode. When the data of the memory cells need not be retained during the low power consumption mode, the operations of the self-refresh control circuit are unnecessary. Owing to not executing refresh, the internal voltage generator may operate with a power enough to compensate an electric power (leakage current) to be consumed by the internal circuit. As a result, the power consumption during the low power consumption mode can be reduced.
The internal voltage is supplied to the internal circuit even during the low power consumption mode. Therefore, the internal circuit can operate immediately after a release from the low power consumption mode.
According to another aspect of the semiconductor memory device in the present invention, the internal voltage generator includes a plurality of units for generating the internal voltage. During the low power consumption mode, a part of the units suspend(s) so that the power consumption during the low power consumption mode can be further reduced.
According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, a stabilized capacitor connected with a power supply line stores a portion of electric charge to be supplied to the power supply line. The semiconductor memory device when receiving a control signal from the exterior, keeps a connection between the power supply line and the stabilized capacitor but disconnects the power supply line and the internal circuit, thereby entering into the low power consumption mode. Therefore, the power consumption of the internal circuit can be reduced to zero during the low power consumption mode. After the release from the low power consumption mode, the voltage corresponding to the electric charge stored in the stabilized capacitor is applied to the internal circuit through the power supply line when the power supply line and the internal circuit are connected. As a result, the semiconductor memory device can operate immediately after the release from the low power consumption mode.
According to another aspect of the semiconductor memory device in the present invention, an internal voltage generator generates an internal voltage upon receipt of a power supply voltage from the exterior. The internal voltage is supplied to the internal circuit through the power supply line. After the release from the low power consumption mode, therefore, the voltage corresponding to the electric charge stored in the stabilized capacitor can be supplied to the internal circuit.
According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, an internal voltage generator generates an internal voltage to be supplied to a predetermined internal circuit, upon receipt of a power supply voltage from the exterior. An internal voltage detector detects the level of the internal voltage and controls the internal voltage generator according to its detection result. The semiconductor memory device receiving a control signal from the exterior, weakens the response of the internal voltage detector, thereby entering to a low power consumption mode. Weakening the response of the internal voltage detector results in lowering the operation frequency of the internal voltage generator to be operated under the control of the internal voltage detector. As a result, the power consumption during the low power consumption mode can be reduced.
According to another mode of the semiconductor memory device of the invention, the internal voltage generator includes a plurality of units for detecting the level of the internal voltage. During the low power consumption mode, a part of the units suspend(s) their operations so that the power consumption during the power consumption mode can be further reduced.
According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, an internal voltage generator generates an internal voltage to be supplied to a predetermined internal circuit, upon receipt of a power supply voltage from the exterior. An internal voltage detector detects the level of the internal voltage and controls the internal voltage generator according to its detection result. The semiconductor memory device receiving a control signal from the exterior, lowers the detection level of the internal voltage in the internal voltage detector and reduces the absolute value of the internal voltage generated by the internal voltage generator, thereby entering into a low power consumption mode. Therefore, the drivability of the internal voltage generator can be lowered, which reduces the power consumption.
According to another aspect of the semiconductor memory device in the present invention, a reference voltage generator generates a reference voltage. The internal voltage detector detects the level of the internal voltage by comparing the internal voltage with the reference voltage. The semiconductor memory device receiving a control signal from the exterior, lowers the level of the reference voltage generated by the reference voltage generator, thereby decreasing the absolute value of the detection level of the internal voltage in the internal voltage detector. This results in reducing the absolute value of the level of the internal voltage and the off current of transistors and so on in the internal circuit, thereby reducing the power consumption.
According to another aspect of the semiconductor memory device and the method of controlling the semiconductor memory device in the present invention, a self-refresh control circuit automatically refreshes memory cells at a predetermined cycle. When the semiconductor memory device receives a control signal from the exterior, it inactivates the self-refresh control circuit and enters into a low power consumption mode. Owing to not executing refresh during the low power consumption mode, a current amount consumed for the refresh can be reduced.
According to another aspect of the semiconductor memory device in the present invention, the self-refresh control circuit includes a timer for determining a length of refresh cycle. The timer suspends during the low power consumption mode so that the power consumption can be reduced.
According to one aspect of a method of controlling the semiconductor memory device in the present invention, the internal voltage generator when activated, generates the internal voltage to be supplied to a predetermined internal circuit. When the internal voltage generator is operated, a predetermined amount of electric power is consumed. In response to the control signal from the exterior, the internal voltage generator is inactivated. The internal voltage is not to be generated due to the inactivation of the internal voltage, which results in reducing the power consumption. In response to the control signal from the exterior, therefore, the device can easily enter the low power consumption mode.
According to another aspect of the method of controlling the semiconductor memory device in the present invention, a plurality of control signals is received from the exterior. The device enters the low power consumption mode when it recognizes the states of the control signals as the low power consumption commands. Therefore, the device can enter the low power consumption mode by the command input.
According to another aspect of the method of controlling the semiconductor memory device in the present invention, when the power supply is switched on, the chip enable signal remains inactivated until the power supply voltage reaches a predetermined voltage. This makes it possible to prevent an erroneous entry to the low power consumption mode when the power supply is switched on.